Contents
7.2.11 R5 Program Page Selection, CNT CLK & Scale Setting, CNT1 Data (L).........20
7.2.11.1 Page 0 Program Page .......................................................................20
7.2.11.2 Page 1 Counter 1 Counter 2 CLK and Scale Setting ........................20
7.2.11.3 Page 2 Counter 1 Low 8-bit Data Buffer............................................21
7.2.11.4 Page 3 DA Control .............................................................................21
7.2.12 R6 Port 6 I/O Data, Data ROM Data Buffer, CNT1 Data (H), DA Control.........22
7.2.12.1 Page 0 Port 6 I/O Data.......................................................................22
7.2.12.2 Page 1 Data ROM Data Buffer ..........................................................22
7.2.12.3 Page 2 Counter 1 High 8-bit Data Buffer...........................................22
7.2.12.4 Page 3 DA Control .............................................................................23
7.2.13 R7 Port 7 I/O Data, Data ROM Address, CNT2 Data, SPI Control...................23
7.2.13.1 Page 0 Port 7 I/O Data.......................................................................23
7.2.13.2 Page 1 Data ROM Address................................................................23
7.2.13.3 Page 2 Counter 2 Data Buffer............................................................24
7.2.13.4 Page 3 SPI Control Register..............................................................24
7.2.14 R8 Port 8 I/O Data, Data ROM Address, DTMF Receiver, SPI Data................28
7.2.14.1 Page 0 Port 8 I/O Data.......................................................................28
7.2.14.2 Page 1 Data ROM address................................................................28
7.2.14.3 Page 2 DTMF Receiver .....................................................................29
7.2.14.4 Page 3 SPI Data Buffer......................................................................31
7.2.15 R9 Port 9 I/O Data, Data ROM Address, Keytone Control................................31
7.2.15.1 Page 0 Port 9 I/O Data.......................................................................31
7.2.15.2 Page 1 Data ROM Address................................................................32
7.2.15.3 Page 2 FSK/CW/DTMF Power Select ...............................................32
7.2.15.4 Page 3 Keytone Control.....................................................................32
7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer Comparator
Control, Tone 1 Generator ................................................................................33
7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer..............33
7.2.16.2 Page 1 Undefined Register................................................................37
7.2.16.3 Page 2 Comparator Control Register ................................................37
7.2.16.4 Page 3 Tone 1 Control Register.........................................................39
7.2.17 RB Port B I/O Data, Key Strobe, Tone 2 Generator..........................................40
7.2.17.1 Page 0 Port B I/O Data ......................................................................40
7.2.17.2 Page 1 Undefined Register................................................................40
7.2.17.3 Page 2 Key Strobe Control Register..................................................40
7.2.17.4 Page 3 Tone 2 Control Register.........................................................40
7.2.18 RC Port C I/O Data, Data RAM Data Buffer, Tone 2 Generator........................41
7.2.18.1 Page 0 Port C I/O Data......................................................................41
7.2.18.2 Page 1 Data RAM Data Buffer 1........................................................41
7.2.18.3 Page 2 Key Strobe Control Register..................................................41
7.2.18.4 Page 3 Undefined Register:...............................................................41
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Product Specification (V2.4) 02.17.2006
ELAN [ ELAN MICROELECTRONICS CORP ]
