EM73P361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TFCFC
TGS
TTCFS
TZS
0101 0011
0101 0100
0101 0010
0101 1011
SF←CF', CF←0
SF←GF
SF←CF, CF←1
SF←ZF
1
1
1
1
1
1
1
1
0
-
1
-
-
-
-
-
*
*
*
*
(12) Interrupt control
Mnemonic Object code ( binary ) Operation description
CIL
Byte
Cycle
Flag
C
-
-
-
-
Z
S
1
1
1
1
*
r
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
IL←IL & r
2
2
2
1
1
2
2
2
1
2
-
-
-
-
*
DICIL r
EICIL r
EXAE
RTI
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
0100 1101
*
(13) CPU control
Mnemonic
NOP
Object code ( binary ) Operation description
0101 0110 no operation
Byte
Cycle
Flag
C
-
Z
S
-
1
1
-
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LDADPL
LDADPM
LDADPH
LDASP
0110 1010 1111 1100
0110 1010 1111 1101
0110 1010 1111 1110
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
0110 1010 1111 0110
0110 1010 1111 1000
0110 1010 1111 1001
0110 1010 1111 1010
0110 1001 1111 1100
0110 1001 1111 1101
0110 1001 1111 1110
0110 1001 1111 1111
0110 1001 1111 0100
0110 1001 1111 0101
0110 1001 1111 0110
0110 1001 1111 1000
0110 1001 1111 1001
0110 1001 1111 1010
Acc←[DP]L
Acc←[DP]M
Acc←[DP]H
Acc←SP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
-
-
-
-
-
LDATAL
LDATAM
LDATAH
LDATBL
LDATBM
LDATBH
STADPL
STADPM
STADPH
STASP
STATAL
STATAM
STATAH
STATBL
STATBM
STATBH
Acc←[TA]L
Acc←[TA]M
Acc←[TA]H
Acc←[TB]L
Acc←[TB]M
Acc←[TB]H
[DP]L←Acc
[DP]M←Acc
[DP]H←Acc
SP←Acc
[TA]L←Acc
[TA]M←Acc
[TA]H←Acc
[ TB]L←Acc
[TB]M←Acc
[TB]H←Acc
-
* This specification are subject to be changed without notice.
12.17.2001
35
ELAN [ ELAN MICROELECTRONICS CORP ]
