EM73P361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
-
-
-
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
Z
S
ANDA #k
ANDAM
ANDM #k
0110 1110 0110 kkkk
0111 1011
0110 1110 1110 kkkk
0110 1110 0100 kkkk
0111 1000
Acc←Acc&k
2
1
2
2
1
2
1
2
1
2
2
1
2
1
-
-
-
-
-
-
-
Z
Z
Z
Z
Z
Z
Z
Z'
Z'
Z'
Z'
Z'
Z'
Z'
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
ORA
#k
ORAM
ORM #k
XORAM
0110 1110 1100 kkkk
0111 1001
(5) Exchange
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
-
-
-
Z
Z
Z
Z
Z
S
1
1
1
1
EXA
x
0110 1000 xxxx xxxx Acc↔RAM[x]
2
1
1
1
2
2
2
1
EXAH
EXAL
EXAM
0110 0110
0110 0100
0101 1000
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
EXHL x
0100 1100 xxxx xx00 LR↔RAM[x],
HR↔RAM[x+1]
2
2
-
-
1
(6) Branch
Mnemonic
SBR a
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
-
Z
-
S
1
00aa aaaa
If SF=1 then PC←PC11-6.a5-0
else null
1
2
1
2
LBR a
1100 aaaa aaaa aaaa
If SF= 1 then PC←a else null
-
-
1
(7) Compare
Mnemonic
Object code ( binary ) Operation description
Byte
Cycle
Flag
C
C
C
C
-
Z
Z
Z
Z
Z
Z
Z
S
CMP #k,y 0100 1011 kkkk yyyy k-RAM[y]
2
2
1
2
1
2
2
2
1
2
1
2
Z'
Z'
Z'
C
Z'
C
CMPA x
CMPAM
0110 1011 xxxx xxxx RAM[x]-Acc
0111 0011 RAM[HL] - Acc
CMPH #k 0110 1110 1011 kkkk k - HR
CMPIA #k 1011 kkkk k - Acc
CMPL #k 0110 1110 0011 kkkk k-LR
C
-
* This specification are subject to be changed without notice.
12.17.2001
33
ELAN [ ELAN MICROELECTRONICS CORP ]
