EM73962A
4-BIT MICROCONTROLLER
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
-
-
-
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Mnemonic
Object code ( binary ) Operation description
Byte Cycle
Flag
C
Z
S
ANDA #k
ANDAM
ANDM #k
0110 1110 0110 kkkk
0111 1011
0110 1110 1110 kkkk
0110 1110 0100 kkkk
0111 1000
Acc←Acc&k
2
1
2
2
1
2
1
2
1
2
2
1
2
1
-
-
-
-
-
-
-
Z
Z
Z
Z
Z
Z
Z
Z'
Z'
Z'
Z'
Z'
Z'
Z'
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
ORA
#k
ORAM
ORM #k
XORAM
0110 1110 1100 kkkk
0111 1001
(5) Exchange
Mnemonic
Object code ( binary ) Operation description
Byte Cycle
Flag
C
-
-
-
-
Z
Z
Z
Z
Z
S
1
1
1
1
EXA
x
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
2
2
1
EXAH
EXAL
EXAM
EXHL x
2
2
-
-
1
(6) Branch
Mnemonic
SBR a
Object code ( binary ) Operation description
Byte Cycle
Flag
C
-
Z
-
S
1
00aa aaaa
If SF=1 then PC←PC12-6.a5-0
elsenull
1
1
LBR a
SLBR a
1100 aaaa aaaa aaaa
0101 0101 1100 aaaa If SF=1 then PC←a else null
aaaa aaaa (a:1000~1FFFh)
If SF= 1 then PC←a else null
2
3
2
3
-
-
-
-
1
1
0101 0111 1100 aaaa
aaaa aaaa (a:0000~0FFFh)
(7) Compare
Mnemonic
Object code ( binary ) Operation description
Byte Cycle
Flag
Z
C
C
C
S
Z'
Z'
CMP #k,y 0100 1011 kkkk yyyy k-RAM[y]
CMPA x 0110 1011 xxxx xxxx RAM[x]-Acc
2
2
2
2
Z
Z
* This specification are subject to be changed without notice.
10.8.2001
32
ELAN [ ELAN MICROELECTRONICS CORP ]
