EM39LV088
8M Bits (1Mx8) Flash Memory
SPECIFICATION
DC CHARACTERISTICS (CMOS Compatible)
Parameter
Description
Test Conditions
Min
Max
Unit
Power Supply Current
Address Input =VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
IDD
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH,
Read
Program and Erase
30
30
mA
mA
ISB
Standby VDD Current
CE#=VIHC, VDD=VDD Max
20
µA
ILI
ILO
Input Leakage Current
Output Leakage Current
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
1
10
µA
µA
VIL
VIH
VIHC
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
VDD=VDD Min
0.8
V
V
V
VDD=VDD Max
0.7 VDD
VDD-0.3
VDD=VDD Max
VOL
VOH
Output Low Voltage
Output High Voltage
IOL=100µA, VDD=VDD Min
IOH=-100µA, VDD=VDD Min
0.2
V
V
VDD-0.2
Table 5: DC Characteristics (Cmos Compatible)
Recommended System Power-up Timing
Parameter
Description
Power-up to Read Operation
Power-up to Program/Erase Operation
Min
100
100
Unit
µs
*
TPU-READ
*
TPU-WRITE
µs
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 6: Recommended System Power-up Timing
Capacitance (Ta=25°C, f=1Mhz, other pins open)
Parameter
Description
I/O Pin Capacitance
Input Capacitance
Test Conditons
VI/O=0V
Max
12pF
6pF
*
CI/O
*
CIN
VIN=0V
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 7: Capacitance (Ta=25°C, f=1Mhz, Other Pins Open)
Reliability Characteristics
Symbol
NEND
Parameter
Endurance
Min Specification
10,000
Unit
Cycles
Years
mA
Test Method
*
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
*
TDR
Data Retention
10
*
ILTH
Latch Up
100+IDD
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 8: Reliability Characteristics
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 9 of 22
ELAN [ ELAN MICROELECTRONICS CORP ]
