EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
DC CHARACTERISTICS (CMOS Compatible)
Parameter
Description
Test Conditions
Min
Max
Unit
Power Supply Current
Address Input =VIL/VIH, at f=1/TRC Min,
V
DD=VDD Max
IDD
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH,
Read
20
30
mA
mA
Program and Erase
ISB
Standby VDD Current
CE#=VIHC, VDD=VDD Max
10
µA
ILI
Input Leakage Current
Output Leakage Current
VIN=GND to VDD, VDD=VDD Max
1
µA
µA
ILO
V
OUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
DD=VDD Max
10
VIL
VIH
Input Low Voltage
0.8
V
V
V
Input High Voltage
V
0.7 VDD
VDD-0.3
VIHC
Input High Voltage (CMOS)
VDD=VDD Max
VOL
VOH
Output Low Voltage
Output High Voltage
IOL=100µA, VDD=VDD Min
IOH=-100µA, VDD=VDD Min
0.2
V
V
VDD-0.2
Table 5: DC Characteristics (Cmos Compatible)
Recommended System Power-up Timing
Parameter
Description
Min
100
100
Unit
µs
*
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
*
TPU-WRITE
µs
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 6: Recommended System Power-up Timing
Capacitance (Ta = 25°C, f = 1Mhz, other pins open)
Parameter
Description
I/O Pin Capacitance
Input Capacitance
Test Conditons
Max
12pF
6pF
*
CI/O
VI/O=0V
*
CIN
VIN=0V
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 7: Capacitance (Ta = 25°C, f = 1Mhz, Other Pins Open)
Reliability Characteristics
Symbol
Parameter
Min Specification
Unit
Test Method
*
NEND
Endurance
10,000
10
Cycles
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
*
TDR
Data Retention
Latch Up
Years
mA
*
ILTH
100+IDD
*This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
Table 8: Reliability Characteristics
This specification is subject to change without further notice. (07.22.2004 V1.0)
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