AG8888
CALL WAITING DECODER
APPLICATION NOTE
1. VDD, GND
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND's.
2. OE pin
Always connect OE to VDD for normal use.
3.
14 OPO
180k
1 TI/RI
C6
R4
100p
R2
C1
R3
C3
TIP
250V
120k
5.6k
4700p
3300p
R6
180k
1N4148
R1
R5
56k
C4
C2
2
3
BO
FI
RING
1M
250V
4700p
0.1u
C5
1N4148
4700p
In the application circuit above , some of the external element values are crucial. C2 value could not be less than
0.1uF. R2 = 5.6k is proper and you had better not to change it. The diode has to use Si type diode for noise
consideration.
There are an OPAmp. External resistors R3 and R4 can adjust the gain of OPAmp. The gain for OPAmp = -R4/
R3.
4. OPO pin
This pin is the gain adjustment of OPAmp. See the partial application above. For high frequency noise immunity,
the user can connect a 100pF capacitor between TI/RI pin and OPO pin.
5. OSCI pin, OSCI pin
The clock generator input XIN pin and output XOUT need to connect a feedback resistor 1M( between them for
proper operation.
6. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due
to the voltage difference between AVDD and DVDD pins when power is ON.
* This specification are subject to be changed without notice.
8.8.2000
7
ELAN [ ELAN MICROELECTRONICS CORP ]
