EBJ21UE8BDS1
Serial PD Matrix
Hex
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments
Number of serial PD bytes written/SPD
device size/CRC coverage
0
1
0
0
1
0
0
1
0
92H
10H
176/256/0-116
Revision 1.0
1
SPD revision
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
0
2
Key byte/DRAM device type
Key byte/module type
0BH DDR3 SDRAM
3
03H
02H
11H
00H
09H
03H
52H
01H
08H
SO-DIMM
4
SDRAM density and banks
SDRAM addressing
1G bits, 8 banks
5
14 rows, 10 columns
6
Module nominal voltage, VDD
Module organization
1.5V
7
2 ranks/×8 bits
8
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
64 bits/non-ECC
9
5/2
1
10
11
8
SDRAM minimum cycle time
12
(tCK (min.))
-DJ
0
0
0
0
1
1
0
0
0CH 1.5ns
-AE
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0FH
00H
1.875ns
13
14
Reserved
—
SDRAM /CAS latencies supported, LSB
-DJ
0
0
1
1
1
1
1
0
3EH CL = 5, 6, 7, 8, 9
1EH CL = 5, 6, 7, 8
-AE
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
15
16
17
18
SDRAM /CAS latencies supported, MSB
00H
69H
78H
69H
—
SDRAM minimum /CAS latencies time
(tAA (min.))
0
0
0
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
13.125ns
15ns
SDRAM write recovery time (tWR (min))
SDRAM minimum /RAS to /CAS delay
(tRCD)
13.125ns
SDRAM minimum row active to row active
19
delay (tRRD)
-DJ
0
0
1
1
0
0
0
0
30H
6ns
-AE
0
0
0
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
0
0
0
1
1
3CH 7.5ns
SDRAM minimum row precharge time
(tRP)
20
21
69H
11H
13.125ns
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
22
(tRAS), LSB
-DJ
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
20H
36ns
-AE
2CH 37.5ns
SDRAM minimum active to active /auto-
refresh time (tRC), LSB
-DJ
23
89H
49.125ns
-AE
1
0
0
1
0
1
1
1
0
0
1
0
0
0
1
0
95H
70H
50.625ns
110ns
SDRAM minimum refresh recovery time
delay (tRFC), LSB
24
25
26
SDRAM minimum refresh recovery time
delay (tRFC), MSB
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
03H
110ns
SDRAM minimum internal write to read
command delay (tWTR)
3CH 7.5ns
Data Sheet E1623E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
