EBJ11UD8CASA, EBJ11UD8BASA
Hex
Byte No. Function described
SDRAM minimum row active to row active
delay (tRRD)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments
19
0
0
1
1
0
0
0
0
30H
6ns
-DG, -DJ
-AC, -AE
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
3CH 7.5ns
-8A, -8C
50H
60H
10ns
12ns
SDRAM minimum row precharge time
(tRP)
-DG
20
0
1
1
0
0
0
0
0
-DJ
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
0
1
0
0
1
1
1
1
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
6CH 13.5ns
5AH 11.25ns
-AC
-AE
69H
64H
78H
11H
13.125ns
12.5ns
15ns
-8A
-8C
21
22
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
(tRAS), LSB
-DG, -DJ
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
20H
36ns
-AC, -AE, -8A, -8C
2CH 37.5ns
80H 48ns
8CH 49.5ns
SDRAM minimum active to active /auto-
refresh time (tRC), LSB
-DG
23
-DJ
-AC
-AE
-8A
-8C
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
1
0
0
86H
95H
90H
48.75ns
50.625ns
50ns
A4H 52.5ns
D0H 90ns
SDRAM minimum refresh recovery time
delay (tRFC), LSB
24
25
26
27
28
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
SDRAM minimum refresh recovery time
delay (tRFC), MSB
0
02H
90ns
SDRAM minimum internal write to read
command delay (tWTR)
1
1
3CH 7.5ns
3CH 7.5ns
SDRAM minimum internal read to
precharge command delay (tRTP)
Upper nibble for tFAW
-DG, -DJ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
00H
01H
-AC, -AE, -8A, -8C
0
1
Minimum four activate window delay time
(tFAW)
29
1
1
1
0
0
0
0
F0H
30ns
-DG, -DJ
-AC, -AE
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
2Ch
40H
03H
37.5ns
40ns
-8A, -8C
30
31
SDRAM output drivers supported
RZQ/6, 7
ASR / 2X refresh,
ODTS
SDRAM refresh options
0
0
0
0
0
1
1
0
0
0CH
32 to 59 Reserved
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
00H
0FH
11H
05H
—
60
61
62
Module nominal height
0
29 < height ≤ 30mm
Module maximum thickness
Reference raw card used
0
0
Raw Card F
Preliminary Data Sheet E1129E10 (Ver. 1.0)
7
ELPIDA [ ELPIDA MEMORY ]
