EBJ11ED8CAFA, EBJ11ED8BAFA
Serial PD Matrix
Hex
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments
Number of serial PD bytes written/SPD
device size/CRC coverage
0
1
0
0
1
0
0
1
0
92H
00H
CRC 0-116/256/176
Revision 0.0
1
SPD revision
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
0
1
1
0
1
1
0
1
0
2
Key byte/DRAM device type
Key byte/module type
0BH DDR3 SDRAM
3
02H
01H
09H
00H
09H
Unbuffered
4
SDRAM density and banks
SDRAM addressing
512M bits, 8 banks
13 rows, 10 columns
—
5
6
Reserved
7
Module organization
2 ranks/×8 bits
8
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
0BH 72 bits / ECC
9
52H
01H
08H
5 / 2
1
10
11
8
SDRAM minimum cycle time
(tCK (min.))
12
0
0
0
0
1
1
0
0
0CH 1.5ns
-DG, -DJ
-AC, -AE
-8A, -8C
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
0
0FH
14H
00H
1.875ns
2.5ns
—
13
14
Reserved
SDRAM /CAS latencies supported, LSB
-DG
0
0
1
1
1
1
1
0
3EH CL = 5, 6, 7, 8, 9
34H CL = 6, 8, 9
-DJ
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
-AC
1EH CL = 5, 6, 7, 8
1CH CL = 6, 7, 8
-AE
-8A
06H
04H
00H
CL = 5, 6
CL = 6
—
-8C
15
16
SDRAM /CAS latencies supported, MSB
SDRAM minimum /CAS latencies time
(tAA (min.))
-DG
0
1
1
0
0
0
0
0
60H
12ns
-DJ
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
6CH 13.5ns
5AH 11.25ns
-AC
-AE
69H
64H
78H
78H
13.125ns
12.5ns
15ns
-8A
-8C
17
18
SDRAM write recovery time (tWR)
15ns
SDRAM minimum /RAS to /CAS delay
(tRCD)
-DG
0
1
1
0
0
0
0
0
60H
12ns
-DJ
-AC
-AE
-8A
-8C
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
1
1
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
6CH 13.5ns
5AH 11.25ns
69H
64H
78H
13.125ns
12.5ns
15ns
Preliminary Data Sheet E1004E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
