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EBJ10UE8BDS0 参数 Datasheet PDF下载

EBJ10UE8BDS0图片预览
型号: EBJ10UE8BDS0
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR3 SDRAM SO- DIMM [1GB DDR3 SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 21 页 / 200 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBJ10UE8BDS0的Datasheet PDF文件第5页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第6页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第7页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第8页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第10页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第11页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第12页浏览型号EBJ10UE8BDS0的Datasheet PDF文件第13页  
EBJ10UE8BDS0  
SPD for Intel Extreme Memory Profile (EBJ10UE8BDS0-GN)  
Hex  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments  
Intel Extreme Memory  
0CH  
176  
177  
Intel extreme memory profile ID string  
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
Profile ID String  
Intel Extreme Memory  
4AH  
Intel extreme memory profile ID string  
Profile ID String  
Profile 1: Enabled /  
Profile 2: Enabled /  
Profile 1: 1 DIMM per  
CH / Profile 2: 1  
DIMM per CH /  
Intel extreme memory profile  
organization type  
178  
0
0
0
0
0
0
1
1
03H  
179  
180  
Intel extreme memory profile revision  
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
11H  
01H  
Revision 1.1  
Medium timebase (MTB) dividend  
for profile 1  
1
Medium timebase (MTB) divisor  
for profile 1  
181  
182  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
08H  
01H  
8
1
8
Medium timebase (MTB) dividend  
for profile 2  
Medium timebase (MTB) divisor  
for profile 2  
183  
184  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
08H  
00H  
Reserved for global byte  
[For Profile 1]  
Hex  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments  
185  
186  
Module VDD voltage level  
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
2AH 1.50V  
SDRAM minimum cycle time  
(tCK (min.))  
0AH DDR3-1600  
SDRAM minimum /CAS latencies time  
(tAA (min.))  
187  
188  
189  
190  
191  
192  
0
1
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
69H  
13.125ns  
SDRAM /CAS latencies supported, LSB  
(CL MASK)  
BCH 6, 7, 8, 9, 11  
00H  
SDRAM /CAS latencies supported, MSB  
(CL MASK)  
Minimum CAS write latency time  
(tCWL(min))  
69H  
69H  
69H  
13.125ns  
13.125ns  
SDRAM minimum row precharge time  
(tRP)  
SDRAM minimum /RAS to /CAS delay  
(tRCD)  
13.125ns  
15ns  
193  
194  
SDRAM write recovery time (tWR (min))  
SDRAM upper nibbles for tRAS and tRC  
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
78H  
11H  
SDRAM minimum active to precharge  
time (tRAS), LSB  
195  
196  
197  
198  
199  
200  
201  
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
0
0
1
0
18H  
86H  
3FH  
00H  
70H  
03H  
35ns  
SDRAM minimum active to active /auto-  
refresh time (tRC), LSB  
48.75ns  
7.8µs  
7.8µs  
110ns  
110ns  
Maximum average periodic refresh interval  
(tREFI), LSB  
Maximum average periodic refresh interval  
(tREFI), MSB  
SDRAM minimum refresh recovery time  
delay (tRFC), LSB  
SDRAM minimum refresh recovery time  
delay (tRFC), MSB  
SDRAM minimum internal read to  
precharge command delay (tRTP)  
3CH 7.5ns  
Preliminary Data Sheet E1512E10 (Ver. 1.0)  
9