EBJ10UE8BDF0
Serial PD Matrix
Hex
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments
Number of serial PD bytes written/SPD
0
device size/CRC coverage
-GN
1
0
0
1
0
0
1
1
93H
256/256/0-116
-DJ, -AE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
92H
10H
176/256/0-116
Revision 1.0
1
SPD revision
2
Key byte/DRAM device type
Key byte/module type
0BH DDR3 SDRAM
3
02H
02H
11H
00H
01H
03H
52H
01H
08H
Unbuffered
4
SDRAM density and banks
SDRAM addressing
1G bits, 8 banks
5
14 rows, 10 columns
6
Module nominal voltage, VDD
Module organization
1.5V
7
1 rank/×8 bits
8
Module memory bus width
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
64 bits/non-ECC
9
5/2
1
10
11
8
SDRAM minimum cycle time
12
(tCK (min.))
-GN
0
0
0
0
1
0
1
0
0AH 1.25ns
0CH 1.5ns
-DJ
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
0
-AE
0FH
00H
1.875ns
—
13
14
Reserved
SDRAM /CAS latencies supported, LSB
-GN
1
0
1
1
1
1
0
0
BCH CL = 6, 7, 8, 9, 11
-DJ
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
3CH CL = 6, 7, 8, 9
1CH CL = 6, 7, 8
-AE
15
16
17
18
SDRAM /CAS latencies supported, MSB
00H
69H
78H
69H
—
SDRAM minimum /CAS latencies time
(tAA (min.))
0
0
0
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
13.125ns
15ns
SDRAM write recovery time (tWR (min))
SDRAM minimum /RAS to /CAS delay
(tRCD)
13.125ns
SDRAM minimum row active to row active
19
delay (tRRD)
-GN, -DJ
0
0
1
1
0
0
0
0
30H
6ns
-AE
0
0
0
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
0
0
0
1
1
3CH 7.5ns
SDRAM minimum row precharge time
(tRP)
20
21
69H
11H
13.125ns
SDRAM upper nibbles for tRAS and tRC
SDRAM minimum active to precharge time
22
(tRAS), LSB
-GN
0
0
0
1
1
0
0
0
18H
20H
35ns
36ns
-DJ
-AE
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
2CH 37.5ns
Preliminary Data Sheet E1514E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
