EBE82FF4A1RQ
Advanced Memory Buffer Block Diagram
Southbound
Data in
Southbound
10×2
Data out
10×2
Reference
clock
Data merge
PLL
RE-time
Re-synch
1×2
Demux
PISO
/RESET
Reset
control
10×12
10×12
Link init SM
and control
and CSRs
Init
patterns
Thermal
sensor
Mux
4
DRAM clock
4
IBIST-RX
LAI logic
DRAM Command
IBIST-TX
failover
DRAM clock
Command
decoder &
CRC check
24
DRAM
address and
Command
out
command copy1
Mux
Mux
24
DRAM
address and
command copy2
DRAM
interface
DDR state controller
and CSRs
Core
controller
and CSRs
A2 for the ECC DRAMs
A6 for the ECC DRAMs
Write data
FIFO
Data out
Data in
4
DRAM chip select
External MemBIST
DDR calibration
72+18×2
DRAM
data and strobes
Sync & idle
pattern
generator
Data CRC
generator and
Read FIFO
NB LAI Buffer
IBIST-TX
IBIST-RX
LAI
controller
Link init SM
and control
and CSRs
Mux
SMBus
failover
SMBus
14×6×2
14×12
controller
PISO
Demux
Re-synch
RE-time
Data merge
Northbound
Data Out
Northbound
14×2
14×2
Data In
Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.
Preliminary Data Sheet E1242E20 (Ver. 2.0)
4
ELPIDA [ ELPIDA MEMORY ]
