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EBE52UD6AJUA-8E-E 参数 Datasheet PDF下载

EBE52UD6AJUA-8E-E图片预览
型号: EBE52UD6AJUA-8E-E
PDF下载: 下载PDF文件 查看货源
内容描述: 512MB DDR2 SDRAM SO- DIMM [512MB DDR2 SDRAM SO-DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 28 页 / 288 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第2页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第3页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第4页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第5页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第7页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第8页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第9页浏览型号EBE52UD6AJUA-8E-E的Datasheet PDF文件第10页  
EBE52UD6AJUA  
Byte No. Function described  
Maximum data access time (tAC) from  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
26  
clock at CL = X 2  
0
1
1
0
0
0
0
0
60H  
0.6ns*1  
-8E, -6E (CL = 3)  
-8G (CL = 4)  
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
50H  
32H  
3CH  
28H  
0.5ns*1  
12.5ns  
15ns  
Minimum row precharge time (tRP)  
-8E  
27  
-8G, -6E  
Minimum row active to row active delay  
28  
29  
10ns  
(tRRD)  
Minimum /RAS to /CAS delay (tRCD)  
-8E  
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
1
0
32H  
3CH  
2DH  
40H  
12.5ns  
15ns  
-8G, -6E  
Minimum active to precharge time  
(tRAS)  
Module rank density  
30  
31  
45ns  
256M bytes  
Address and command setup time  
before clock (tIS)  
32  
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
0
1
17H  
20H  
25H  
0.17ns*1  
0.20ns*1  
0.25ns*1  
-8E, -8G  
-6E  
Address and command hold time after  
clock (tIH)  
-8E, -8G  
33  
-6E  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
27H  
05H  
10H  
12H  
0.27ns*1  
0.05ns*1  
0.10ns*1  
0.12ns*1  
Data input setup time before clock (tDS)  
-8E, -8G  
-6E  
Data input hold time after clock (tDH)  
-8E, -8G  
-6E  
34  
35  
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
17H  
3CH  
0.17ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
Memory analysis probe characteristics  
Extension of Byte 41 and 42  
-8E  
-8G, -6E  
Active command period (tRC)  
-8E  
-8G, -6E  
Auto refresh to active/  
Auto refresh command cycle (tRFC)  
38  
39  
40  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1EH  
00H  
30H  
00H  
39H  
3CH  
69H  
80H  
14H  
18H  
1EH  
7.5ns*1  
TBD  
Undefined  
57.5ns*1  
60ns*1  
41  
42  
43  
44  
105ns*1  
8ns*1  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-8E, -8G  
0.20ns*1  
0.24ns*1  
0.30ns*1  
-6E  
Data hold skew (tQHS)  
-8E, -8G  
-6E  
45  
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
22H  
00H  
00H  
0.34ns*1  
46  
PLL relock time  
Undefined  
Undefined  
47 to 61  
Data Sheet E1084E30 (Ver. 3.0)  
6