EBE52UD6AFSA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
25
26
27
28
29
30
31
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
50H
60H
3CH
28H
3CH
2DH
40H
5.0ns*1
0.6ns*1
15ns
10ns
15ns
45ns
Module rank density
256M bytes
Address and command setup time
32
before clock (tIS)
-6E
0
0
1
0
0
0
0
0
20H
0.20ns*1
-5C
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
25H
35H
0.25ns*1
0.35ns*1
-4A
Address and command hold time after
clock (tIH)
-6E
33
0
0
1
0
1
0
0
0
28H
0.28ns*1
-5C
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
0
38H
48H
0.38ns*1
0.48ns*1
-4A
Data input setup time before clock
34
35
(tDS)
0
0
0
1
0
0
0
0
10H
0.10ns*1
-6E, -5C
-4A
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
15H
18H
0.15ns*1
0.18ns*1
Data input hold time after clock (tDH)
-6E
-5C
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
0
23H
28H
3CH
0.23ns*1
0.28ns*1
15ns*1
-4A
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-6E, -5C
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
Internal read to precharge command
delay (tRTP)
38
39
40
41
Memory analysis probe characteristics 0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
00H
00H
3CH
TBD
Extension of Byte 41 and 42
0
0
Undefined
60ns*1
Active command period (tRC)
Auto refresh to active/
42
43
44
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
69H
80H
18H
105ns*1
8ns*1
Auto refresh command cycle (tRFC)
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6E
0.24ns*1
-5C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1EH
23H
0.30ns*1
0.35ns*1
-4A
Data Sheet E0722E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
