欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBE52UD6ABSA-5C 参数 Datasheet PDF下载

EBE52UD6ABSA-5C图片预览
型号: EBE52UD6ABSA-5C
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 64MX64, 0.5ns, CMOS, SODIMM-200]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 188 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第5页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第6页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第7页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第8页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第10页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第11页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第12页浏览型号EBE52UD6ABSA-5C的Datasheet PDF文件第13页  
EBE52UD6ABSA  
Electrical Specifications  
All voltages are referenced to VSS (GND).  
Absolute Maximum Ratings  
Parameter  
Symbol  
Value  
Unit  
Note  
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
VT  
–0.5 to +2.3  
–0.5 to +2.3  
50  
V
VDD, VDDQ  
V
IO  
mA  
W
°C  
°C  
PD  
TC  
Tstg  
4
Operating case temperature  
Storage temperature  
0 to +85  
–55 to +150  
1
Note: DDR2 SDRAM component specification.  
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
DC Operating Conditions (TC = 0 to +85°C) (DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
VDD,VDDQ  
VSS  
min  
typ  
1.8  
0
max  
1.9  
0
Unit  
V
Notes  
1
Supply voltage  
1.7  
0
V
VDDSPD  
VREF  
1.8  
3.6  
V
Input reference voltage  
Termination voltage  
Input high voltage  
Input low voltage  
0.49 × VDDQ  
VREF – 0.04  
VREF + 0.125  
–0.3  
0.50 × VDDQ 0.51 × VDDQ  
V
VTT  
VREF  
VREF + 0.04  
VDDQ + 0.3  
VREF – 0.125  
V
VIH (DC)  
VIL (DC)  
V
2
3
V
Input voltage level,  
CK and /CK inputs  
VIN (DC)  
VIX (DC)  
VID (DC)  
–0.3  
VDDQ + 0.3  
V
V
V
4
Input differential cross point  
voltage, CK and /CK inputs  
0.5 × VDDQ 0.1V 0.5 × VDDQ  
0.3  
0.5 × VDDQ + 0.1V  
VDDQ + 0.4  
Input differential voltage,  
CK and /CK inputs  
5, 6  
Notes: 1. VDDQ must be lower than or equal to VDD.  
2. VIH is allowed to exceed VDD up to 2.3V for the period shorter than or equal to 5ns.  
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.  
4. VIN (DC) specifies the allowable DC execution of each differential input.  
5. VID (DC) specifies the input differential voltage required for switching.  
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V  
if measurement.  
Preliminary Data Sheet E0418E10 (Ver. 1.0)  
9