EBE51UD8AJWA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
128 bytes
256 bytes
Total number of bytes in serial PD
device
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
08H
0EH
0AH
60H
40H
00H
05H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
10
1
64
Module data width continuation
0
Voltage interface level of this assembly 0
SSTL 1.8V
DDR SDRAM cycle time, CL = X
-8E (CL = 5)
9
0
0
1
0
0
1
0
1
25H
2.5ns*1
-8G (CL = 6)
-6E (CL = 5)
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
25H
30H
2.5ns*1
3.0ns*1
SDRAM access from clock (tAC)
-8E, -8G
10
0
1
0
0
0
0
0
0
40H
0.4ns*1
-6E
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
45H
00H
82H
08H
00H
00H
0.45ns*1
None.
7.8µs
× 8
11
12
13
14
15
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
None.
0
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH
04H
38H
4,8
SDRAM device attributes: Number of
banks on SDRAM device
4
SDRAM device attributes: /CAS latency
-8E, -6E
3, 4, 5
-8G
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
70H
01H
02H
00H
4, 5, 6
19
20
21
DIMM Mechanical Characteristics
DIMM type information
SDRAM module attributes
4.00mm max.
Unbuffered
Normal
Weak Driver 50Ω
ODT Support
22
23
SDRAM device attributes: General
0
0
0
0
0
0
1
1
03H
Minimum clock cycle time at CL = X − 1
-8E, -6E (CL = 4)
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
0
3DH
30H
3.75ns*1
3.0ns*1
-8G (CL = 5)
Maximum data access time (tAC) from
clock at CL = X − 1
-8E, -6E (CL = 4)
24
25
26
0
1
0
1
0
0
0
0
50H
0.5ns*1
-8G (CL = 5)
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
45H
50H
3DH
0.45ns*1
5.0ns*1
Minimum clock cycle time at CL = X − 2
-8E, -6E (CL = 3)
-8G (CL = 4)
3.75ns*1
Maximum data access time (tAC) from
clock at CL = X − 2
-8E, -6E (CL = 3)
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H
50H
0.6ns*1
0.5ns*1
-8G (CL = 4)
Data Sheet E01053E30 (Ver. 3.0)
5
ELPIDA [ ELPIDA MEMORY ]
