EBE51UD8AEFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
15ns
27
28
29
Minimum row precharge time (tRP)
Minimum row active to row active delay
(tRRD)
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
3CH
1EH
3CH
7.5ns
15ns
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
-5C
30
0
0
1
0
1
1
0
1
2DH
45ns
-4A
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
28H
80H
40ns
31
32
Module rank density
512M bytes
Address and command setup time
before clock (tIS)
-5C
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
0
25H
35H
38H
0.25ns*1
0.35ns*1
0.38ns*1
-4A
Address and command hold time after
clock (tIH)
-5C
33
-4A
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
48H
10H
15H
23H
0.48ns*1
0.10ns*1
0.15ns*1
0.23ns*1
Data input setup time before clock (tDS)
-5C
-4A
Data input hold time after clock (tDH)
-5C
-4A
34
35
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H
3CH
0.28ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-5C
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe characteristics
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H
00H
TBD
Extension of Byte 41 and 42
Undefined
Active command period (tRC)
-5C
-4A
Auto refresh to active/
Auto refresh command cycle (tRFC)
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-5C
41
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
3CH
37H
69H
80H
1EH
23H
28H
60ns*1
55ns*1
42
43
44
105ns*1
8ns*1
0.30ns*1
0.35ns*1
0.40ns*1
-4A
Data hold skew (tQHS)
-5C
-4A
45
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
2DH
00H
00H
0.45ns*1
46
PLL relock time
Undefined
47 to 61
Data Sheet E0584E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
