EBE51RD8ABFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
15ns
Minimum row precharge time (tRP)
27
28
29
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
3CH
1EH
3CH
-5C, -4A
Minimum row active to row active
delay (tRRD)
7.5ns
15ns
Minimum /RAS to /CAS delay (tRCD)
-5C, -4A
Minimum active to precharge time
(tRAS)
30
31
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
2DH
80H
45ns
Module rank density
512M byte
Address and command setup time
before clock (tIS)
-5C
32
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H
35H
38H
48H
10H
0.25ns*1
0.35ns*1
0.38ns*1
0.48ns*1
0.10ns*1
-4A
Address and command hold time after
clock (tIH)
33
-5C
-4A
Data input setup time before clock
(tDS)
-5C
34
35
-4A
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H
23H
0.15ns*1
0.23ns*1
Data input hold time after clock (tDH)
-5C
-4A
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H
3CH
0.28ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-5C
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe characteristics 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H
00H
TBD
Extension of Byte 41 and 42
0
0
Undefined
Active command period (tRC)
-5C, -4A
41
0
1
1
1
1
0
0
3CH
60ns*1
Auto refresh to active/
Auto refresh command cycle (tRFC)
42
43
44
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
69H
80H
1EH
23H
28H
105ns*1
8ns*1
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-5C
0.30ns*1
0.35ns*1
0.40ns*1
-4A
Data hold skew (tQHS)
-5C
45
-4A
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
2DH
0FH
00H
0.45ns*1
46
PLL relock time
15µs
47 to 61
Data Sheet E0402E40 (Ver. 4.0)
6
ELPIDA [ ELPIDA MEMORY ]
