EBE51ED8AEFA-6
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
128 bytes
256 bytes
Total number of bytes in serial PD
device
2
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
08H
0EH
0AH
60H
48H
00H
05H
30H
45H
02H
82H
08H
08H
00H
DDR2 SDRAM
3
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
4
10
5
1
6
72
7
Module data width continuation
0
8
Voltage interface level of this assembly 0
SSTL 1.8V
3.0ns*1
0.45ns*1
ECC
7.8µs
× 8
9
DDR SDRAM cycle time, CL = 5
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
0
0
0
1
0
0
0
10
11
12
13
14
15
Primary SDRAM width
Error checking SDRAM width
Reserved
× 8
0
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH
04H
38H
4,8
SDRAM device attributes: Number of
banks on SDRAM device
4
SDRAM device attributes:
/CAS latency
3, 4, 5
19
20
21
DIMM Mechanical Characteristics
DIMM type information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
01H
02H
00H
4.00mm max.
Unbuffered
Normal
SDRAM module attributes
Weak Driver
50ΩODT Support
22
23
24
25
26
27
28
29
30
31
32
SDRAM device attributes: General
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
0
1
1
1
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
03H
3DH
50H
50H
60H
3CH
1EH
3CH
2DH
80H
20H
Minimum clock cycle time at CL = 4
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
Maximum data access time (tAC) from
clock at CL = 4
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
7.5ns
Minimum /RAS to /CAS delay (tRCD)
15ns
Minimum active to precharge time
(tRAS)
45ns
Module rank density
512M bytes
0.20ns*1
Address and command setup time
before clock (tIS)
Address and command hold time after
clock (tIH)
33
0
0
1
0
1
0
0
0
28H
0.28ns*1
Data input setup time before clock
(tDS)
34
35
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
10H
18H
0.10ns*1
0.18ns*1
Data input hold time after clock (tDH)
Data Sheet E0724E10 (Ver. 1.0)
5
ELPIDA [ ELPIDA MEMORY ]
