EBE25UC8AAFV
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
256 bytes
device
2
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
08H
0DH
0AH
60H
40H
00H
05H
3DH
50H
00H
82H
08H
00H
00H
DDR2 SDRAM
3
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
4
10
5
1
6
64
7
Module data width continuation
0
8
Voltage interface level of this assembly 0
SSTL 1.8V
3.75ns*1
0.5ns*1
None.
7.8µs
× 8
9
DDR SDRAM cycle time, CL = 5
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
0
0
0
1
0
0
0
10
11
12
13
14
15
Primary SDRAM width
Error checking SDRAM width
Reserved
None.
0
SDRAM device attributes:
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH
04H
38H
4,8
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
4
3, 4, 5
19
20
21
22
23
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
00H
02H
00H
30H
3DH
0
DIMM type information
Unbuffered
Normal
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 4
VDD ± 0.1V
3.75ns*1
Maximum data access time (tAC) from
clock at CL = 4
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
Module rank density
24
25
26
27
28
29
30
31
32
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
50H
50H
60H
3CH
1EH
3CH
2DH
40H
25H
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
256M bytes
0.25ns*1
Address and command setup time
before clock (tIS)
Address and command hold time after
clock (tIH)
33
0
0
1
1
1
0
0
0
38H
0.38ns*1
Data input setup time before clock
34
35
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
10H
23H
0.10ns*1
0.23ns*1
(tDS)
Data input hold time after clock (tDH)
Preliminary Data Sheet E0527E12 (Ver. 1.2)
5
ELPIDA [ ELPIDA MEMORY ]
