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EBE25EC8AAFA-4A-E 参数 Datasheet PDF下载

EBE25EC8AAFA-4A-E图片预览
型号: EBE25EC8AAFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB无缓冲DDR2 SDRAM DIMM [256MB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 22 页 / 191 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第2页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第3页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第4页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第5页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第7页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第8页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第9页浏览型号EBE25EC8AAFA-4A-E的Datasheet PDF文件第10页  
EBE25EC8AAFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
Minimum row precharge time (tRP)  
27  
0
0
0
0
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
3CH  
50H  
1EH  
15ns  
20ns  
7.5ns  
-5C, -4A  
-4C  
Minimum row active to row active  
delay (tRRD)  
28  
29  
Minimum /RAS to /CAS delay (tRCD)  
-5C, -4A  
0
0
0
0
0
1
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
3CH  
50H  
2DH  
40H  
15ns  
-4C  
20ns  
Minimum active to precharge time  
(tRAS)  
30  
31  
45ns  
Module rank density  
256M bytes  
Address and command setup time  
before clock (tIS)  
-5C  
32  
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H  
35H  
38H  
48H  
10H  
0.25ns*1  
0.35ns*1  
0.38ns*1  
0.48ns*1  
0.10ns*1  
-4A, -4C  
Address and command hold time after  
clock (tIH)  
-5C  
33  
-4A, -4C  
Data input setup time before clock  
(tDS)  
-5C  
34  
35  
-4A, -4C  
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H  
23H  
0.15ns*1  
0.23ns*1  
Data input hold time after clock (tDH)  
-5C  
-4A, -4C  
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H  
3CH  
0.28ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
-5C  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-4A, -4C  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
Memory analysis probe characteristics 0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H  
00H  
TBD  
Extension of Byte 41 and 42  
0
0
0
0
1
0
0
0
Undefined  
Active command period (tRC)  
-5C, -4A,  
41  
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
3CH  
41H  
4BH  
80H  
1EH  
23H  
28H  
60ns*1  
65ns*1  
75ns*1  
8ns*1  
-4C  
Auto refresh to active/  
42  
43  
44  
Auto refresh command cycle (tRFC)  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-5C  
0.30ns*1  
0.35ns*1  
0.40ns*1  
-4A, -4C  
Data hold skew (tQHS)  
-5C  
45  
-4A, -4C  
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
2DH  
00H  
00H  
0.45ns*1  
46  
PLL relock time  
Undefined  
47 to 61  
Preliminary Data Sheet E0466E10 (Ver. 1.0)  
6