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EBE21UE8ABFA-4A-E 参数 Datasheet PDF下载

EBE21UE8ABFA-4A-E图片预览
型号: EBE21UE8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB无缓冲DDR2 SDRAM DIMM [2GB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 27 页 / 213 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第2页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第3页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第4页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第5页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第7页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第8页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第9页浏览型号EBE21UE8ABFA-4A-E的Datasheet PDF文件第10页  
EBE21UE8ABFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Minimum row precharge time (tRP)  
-8E  
27  
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
32H  
3CH  
1EH  
12.5ns  
15ns  
-6E, -5C, -4A  
Minimum row active to row active  
delay (tRRD)  
28  
29  
7.5ns  
Minimum /RAS to /CAS delay (tRCD)  
-8E  
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
0
32H  
3CH  
12.5ns  
15ns  
-6E, -5C, -4A  
Minimum active to precharge time  
(tRAS)  
30  
0
0
1
0
1
1
0
1
2DH  
45ns  
-8E, -6E, -5C  
-4A  
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
28H  
01H  
40ns  
31  
32  
Module rank density  
1G bytes  
Address and command setup time  
before clock (tIS)  
-8E  
0
0
0
1
0
1
1
1
17H  
0.17ns*1  
-6E  
-5C  
-4A  
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
20H  
25H  
35H  
0.20ns*1  
0.25ns*1  
0.35ns*1  
Address and command hold time  
after clock (tIH)  
-8E  
33  
0
0
1
0
0
1
0
1
25H  
0.25ns*1  
-6E  
-5C  
-4A  
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
27H  
37H  
47H  
0.27ns*1  
0.37ns*1  
0.47ns*1  
Data input setup time before clock  
(tDS)  
-8E  
34  
35  
0
0
0
0
0
1
0
1
05H  
0.05ns*1  
-6E, -5C  
-4A  
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
10H  
15H  
0.10ns*1  
0.15ns*1  
Data input hold time after clock (tDH)  
-8E  
0
0
0
1
0
0
1
0
12H  
0.12ns*1  
-6E  
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
0
17H  
22H  
27H  
3CH  
0.17ns*1  
0.22ns*1  
0.27ns*1  
15ns*1  
-5C  
-4A  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-8E, -6E, -5C  
-4A  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
Memory analysis probe  
characteristics  
0
0
0
0
0
0
0
0
00H  
TBD  
Extension of Byte 41 and 42  
-8E  
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
1
1
0
1
1
0
0
0
1
36H  
06H  
39H  
-6E, -5C, -4A  
Active command period (tRC)  
-8E  
41  
57.5ns*1  
-6E, -5C  
-4A  
0
0
0
0
1
1
1
1
1
0
1
1
0
1
0
1
3CH  
37H  
60ns*1  
55ns*1  
Preliminary Data Sheet E0906E10 (Ver. 1.0)  
6