EBE20RE4ABFA
Byte No. Function described
Minimum active to precharge time
(tRAS)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
30
0
0
1
0
1
1
0
1
2DH
45ns
-6E, -5C
-4A
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
28H
02H
40ns
2GB
31
32
Module rank density
Address and command setup time
before clock (tIS)
-6E
0
0
1
0
0
0
0
0
20H
0.20ns*1
-5C
-4A
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
25H
35H
0.25ns*1
0.35ns*1
Address and command hold time after
clock (tIH)
-6E
33
0
0
1
0
0
1
1
1
27H
0.27ns*1
-5C
-4A
0
0
0
1
1
0
1
0
0
0
1
1
1
1
1
1
37H
47H
0.37ns*1
0.47ns*1
Data input setup time before clock
(tDS)
34
35
0
0
0
1
0
0
0
0
10H
0.10ns*1
-6E, -5C
-4A
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
15H
17H
0.15ns*1
0.17ns*1
Data input hold time after clock (tDH)
-6E
-5C
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
22H
27H
3CH
0.22ns*1
0.27ns*1
15ns*1
-4A
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-6E, -5C
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
TBD
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe characteristics 0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
00H
06H
Extension of Byte 41 and 42
0
0
0
0
1
0
Active command period (tRC)
-6E, -5C
41
0
0
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
3CH
37H
7FH
80H
18H
60ns*1
-4A
55ns*1
Auto refresh to active/
Auto refresh command cycle (tRFC)
42
43
44
127.5ns*1
8ns*1
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6E
0.24ns*1
-5C
-4A
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
1EH
23H
0.30ns*1
0.35ns*1
Data hold skew (tQHS)
-6E
45
0
0
1
0
0
0
1
0
22H
0.34ns*1
-5C
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
1
0
0
28H
2DH
0FH
00H
12H
0.40ns*1
0.45ns*1
15µs
-4A
46
PLL relock time
47 to 61
62
SPD Revision
Rev. 1.2
Data Sheet E0873E40 (Ver. 4.0)
6