EBE20AE4ABFA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
128 bytes
256 bytes
Total number of bytes in serial PD
device
2
3
4
5
6
7
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
08H
0EH
0BH
60H
48H
00H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
11
1
72
0
Module data width continuation
Voltage interface level of this
assembly
8
0
0
0
0
0
1
0
1
05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = 5
SDRAM access from clock (tAC)
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
1
30H
45H
3.0ns*1
0.45ns*1
10
ECC, Address/
11
DIMM configuration type
0
0
0
0
0
1
1
0
06H
Command Parity
12
13
14
15
Refresh rate/type
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
82H
04H
04H
00H
7.8µs
× 4
× 4
0
Primary SDRAM width
Error checking SDRAM width
Reserved
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0CH
08H
38H
4,8
SDRAM device attributes: Number
of banks on SDRAM device
8
SDRAM device attributes:
/CAS latency
3, 4, 5
19
20
21
DIMM Mechanical Characteristics
DIMM type information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
01H
01H
00H
4.00mm max.
Registered
Normal
SDRAM module attributes
Weak Driver
50Ω ODT Support
22
23
24
25
26
27
28
SDRAM device attributes: General 0
Minimum clock cycle time at CL = 4 0
0
0
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
1
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
03H
3DH
50H
50H
60H
3CH
1EH
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
Maximum data access time (tAC)
from clock at CL = 4
0
Minimum clock cycle time at CL = 3 0
Maximum data access time (tAC)
from clock at CL = 3
0
Minimum row precharge time (tRP)
0
0
Minimum row active to row active
delay (tRRD)
7.5ns
Minimum /RAS to /CAS delay
(tRCD)
29
0
0
1
1
1
1
0
0
3CH
15ns
Minimum active to precharge time
(tRAS)
30
31
32
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
2DH
02H
20H
45ns
Module rank density
2GB
Address and command setup time
before clock (tIS)
0.20ns*1
Address and command hold time
after clock (tIH)
33
34
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
27H
10H
0.27ns*1
0.10ns*1
Data input setup time before clock
(tDS)
Data Sheet E0875E30 (Ver. 3.0)
5
ELPIDA [ ELPIDA MEMORY ]
