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EBE11UD8AHFA 参数 Datasheet PDF下载

EBE11UD8AHFA图片预览
型号: EBE11UD8AHFA
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM [1GB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 182 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE11UD8AHFA的Datasheet PDF文件第2页浏览型号EBE11UD8AHFA的Datasheet PDF文件第3页浏览型号EBE11UD8AHFA的Datasheet PDF文件第4页浏览型号EBE11UD8AHFA的Datasheet PDF文件第5页浏览型号EBE11UD8AHFA的Datasheet PDF文件第7页浏览型号EBE11UD8AHFA的Datasheet PDF文件第8页浏览型号EBE11UD8AHFA的Datasheet PDF文件第9页浏览型号EBE11UD8AHFA的Datasheet PDF文件第10页  
EBE11UD8AHFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Minimum row precharge time (tRP)  
-8E  
27  
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
32H  
3CH  
1EH  
12.5ns  
15ns  
-8G  
Minimum row active to row active delay  
(tRRD)  
28  
29  
7.5ns  
Minimum /RAS to /CAS delay (tRCD)  
-8E  
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
0
0
1
0
1
32H  
3CH  
2DH  
80H  
17H  
12.5ns  
15ns  
-8G  
Minimum active to precharge time  
(tRAS)  
30  
31  
32  
45ns  
Module rank density  
512M bytes  
0.17ns*1  
Address and command setup time  
before clock (tIS)  
Address and command hold time after  
clock (tIH)  
33  
34  
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
25H  
05H  
0.25ns*1  
0.05ns*1  
Data input setup time before clock  
(tDS)  
35  
36  
Data input hold time after clock (tDH)  
Write recovery time (tWR)  
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
12H  
3CH  
0.12ns*1  
15ns*1  
Internal write to read command delay  
(tWTR)  
37  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1EH  
00H  
30H  
00H  
39H  
3CH  
69H  
7.5ns*1  
TBD  
Memory analysis probe characteristics  
Extension of Byte 41 and 42  
-8E  
-8G  
Undefined  
57.5ns*1  
60ns*1  
Active command period (tRC)  
-8E  
41  
42  
-8G  
Auto refresh to active/  
Auto refresh command cycle (tRFC)  
105ns*1  
43  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
80H  
14H  
1EH  
00H  
00H  
12H  
8ns*1  
44  
0.20ns*1  
0.30ns*1  
Undefined  
Undefined  
Rev. 1.2  
45  
Data hold skew (tQHS)  
PLL relock time  
46  
47 to 61  
62  
SPD Revision  
Checksum for bytes 0 to 62  
-8E  
63  
0
1
0
1
1
0
0
0
58H  
-8G  
0
0
1
0
×
0
0
0
0
0
0
1
1
0
×
1
1
1
0
0
1
1
1
0
×
0
0
0
1
1
1
1
1
0
×
0
0
0
1
1
1
1
1
0
×
0
0
0
0
0
1
1
1
0
×
1
0
1
0
0
0
1
1
0
×
0
1
0
0
0
0
1
0
0
×
1
0
1
1
1
3CH  
7FH  
FEH  
00H  
××  
64 to 65  
66  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
Manufacturing location  
Module part number  
Continuation code  
Elpida Memory  
67 to 71  
72  
(ASCII-8bit code)  
73  
45H  
42H  
45H  
31H  
31H  
E
B
E
1
74  
Module part number  
75  
Module part number  
76  
Module part number  
77  
Module part number  
1
Prelinary Data Sheet E0941E10 (Ver. 1.0)  
6