EBE11UD8AJUA
Hex
Byte No. Function described
Maximum data access time (tAC) from
clock at CL = X − 2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments
0.6ns*1
26
0
1
1
0
0
0
0
0
60H
-8E, -6E (CL = 3)
-8G (CL = 4)
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
50H
32H
3CH
1EH
0.5ns*1
12.5ns
15ns
Minimum row precharge time (tRP)
-8E
27
-8G, -6E
Minimum row active to row active
delay (tRRD)
28
29
7.5ns
Minimum /RAS to /CAS delay (tRCD)
-8E
0
0
0
1
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
1
0
32H
3CH
2DH
80H
12.5ns
15ns
-8G, -6E
Minimum active to precharge time
(tRAS)
30
31
45ns
Module rank density
512M bytes
Address and command setup time
before clock (tIS)
-8E, -8G
32
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
17H
20H
25H
27H
05H
0.17ns*1
0.20ns*1
0.25ns*1
0.27ns*1
0.05ns*1
-6E
Address and command hold time after
clock (tIH)
-8E, -8G
33
-6E
Data input setup time before clock
(tDS)
-8E, -8G
34
35
-6E
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
10H
12H
0.10ns*1
0.12ns*1
Data input hold time after clock (tDH)
-8E, -8G
-6E
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
17H
3CH
0.17ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
0
0
0
0
1
1
1
1
0
1EH
7.5ns*1
Internal read to precharge command
delay (tRTP)
38
39
40
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1EH
00H
30H
00H
39H
3CH
69H
80H
14H
18H
1EH
7.5ns*1
TBD
Memory analysis probe characteristics 0
Extension of Byte 41 and 42
-8E
0
-8G, -6E
0
0
0
0
1
0
0
0
Undefined
57.5ns*1
60ns*1
Active command period (tRC)
-8E
41
-8G, -6E
Auto refresh to active/
Auto refresh command cycle (tRFC)
42
43
44
105ns*1
8ns*1
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-8E, -8G
0.20ns*1
0.24ns*1
0.30ns*1
-6E
Data hold skew (tQHS)
-8E, -8G
45
46
-6E
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
22H
00H
0.34ns*1
PLL relock time
Undefined
Data Sheet E1083E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
