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EBE11ED8ABFA-4A-E 参数 Datasheet PDF下载

EBE11ED8ABFA-4A-E图片预览
型号: EBE11ED8ABFA-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR2 SDRAM DIMM ( 128M字× 72位, 2级) [1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 22 页 / 174 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第1页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第2页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第3页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第4页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第6页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第7页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第8页浏览型号EBE11ED8ABFA-4A-E的Datasheet PDF文件第9页  
EBE11ED8ABFA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
device  
256 bytes  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
08H  
0EH  
0AH  
61H  
48H  
00H  
05H  
DDR2 SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
14  
10  
2
72  
Module data width continuation  
0
Voltage interface level of this assembly 0  
SSTL 1.8V  
DDR SDRAM cycle time, CL = 5  
9
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
3DH  
50H  
50H  
3.75ns*1  
5.0ns*1  
0.5ns*1  
-5C  
-4A  
0
0
SDRAM access from clock (tAC)  
-5C  
10  
-4A  
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
60H  
02H  
82H  
08H  
08H  
00H  
0.6ns*1  
ECC  
7.8µs  
× 8  
11  
12  
13  
14  
15  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
Reserved  
× 8  
0
SDRAM device attributes:  
Burst length supported  
16  
17  
18  
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH  
04H  
38H  
4,8  
SDRAM device attributes: Number of  
banks on SDRAM device  
4
SDRAM device attributes:  
/CAS latency  
3, 4, 5  
19  
20  
21  
22  
Reserved  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
00H  
02H  
00H  
30H  
0
DIMM type information  
SDRAM module attributes  
SDRAM device attributes: General  
Unbuffered  
Normal  
VDD ± 0.1V  
Minimum clock cycle time at CL = 4  
-5C  
23  
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH  
50H  
3.75ns*1  
5.0ns*1  
-4A  
Maximum data access time (tAC) from  
clock at CL = 4  
-5C  
24  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
-4A  
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H  
50H  
0.6ns*1  
5.0ns*1  
Minimum clock cycle time at CL = 3  
-5C, -4A  
25  
26  
27  
Maximum data access time (tAC) from  
clock at CL = 3  
-5C, -4A  
0
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
60H  
3CH  
0.6ns*1  
15ns  
Minimum row precharge time (tRP)  
-5C, -4A  
Data Sheet E0379E40 (Ver. 4.0)  
5