EBD64UB6ALF
Pin Functions (1)
CLK, /CLK (input pin): The CLK and the /CLK are the master clock inputs. All inputs except DMs, DQSs and DQs
are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs
are referred to the cross point of the CLK and the /CLK. When a write operation, DMs and DQs are referred to the
cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and
the /CLK.
/CS (input pin): When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored.
However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of
the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded
via the A0 to the A8 at the cross point of the CLK rising edge and the VREF level in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write
command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low
when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High
when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is
disabled.
BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2
and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If
BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected.
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are
entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CLK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the
CLK rising edge and the VREF level with proper setup time tIS, at the next CLK rising edge CKE level must be kept
with proper hold time tIH.
Pin Functions (2)
DQ (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input).
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of
DQS and VREF
VDD and VDDQ (power supply pins): 2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output
buffer.)
VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM).
VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Series datasheet (E0136E).
Preliminary Data Sheet E0217E10 (Ver. 1.0)
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ELPIDA [ ELPIDA MEMORY ]
