EBD52EC8AAFA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
256 bytes
device
2
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
07H
0DH
0AH
02H
48H
00H
04H
75H
75H
02H
82H
08H
08H
DDR SDRAM
3
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
4
10
5
2
6
72 bits
0
7
Module data width continuation
8
Voltage interface level of this assembly 0
SSTL2
7.5ns
0.75ns
ECC
7.6µs
× 8
9
DDR SDRAM cycle time, CL = 2.5
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
0
0
0
1
0
0
10
11
12
13
14
Primary SDRAM width
Error checking SDRAM width
× 8
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0EH
04H
0CH
01H
02H
20H
2,4,8
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
4
2, 2.5
0
1
Differential
Clock
SDRAM module attributes
22
23
SDRAM device attributes: General
Minimum clock cycle time at CL = 2
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
C0H
A0H
VDD ± 0.2V
10ns
Maximum data access time (tAC) from
clock at CL = 2
24
0
1
1
1
0
1
0
1
75H
0.75ns
25 to 26
27
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
00H
50H
Minimum row precharge time (tRP)
20ns
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
(tRAS)
Module rank density
28
29
30
31
32
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
3CH
50H
2DH
40H
90H
15ns
20ns
45ns
256M bytes
0.9ns*1
Address and command setup time
before clock (tIS)
Address and command hold time after
clock (tIH)
33
1
0
0
1
0
0
0
0
90H
0.9ns*1
Data Sheet E0363E20 (Ver. 2.0)
5
ELPIDA [ ELPIDA MEMORY ]
