EBD52UC8AMFA-5
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
device
256 bytes
2
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
07H
0DH
0AH
02H
40H
00H
04H
50H
70H
00H
82H
08H
00H
DDR SDRAM
3
Number of row address
Number of column address
Number of DIMM ranks
Module data width
13
4
10
5
2
6
64
7
Module data width continuation
0
8
Voltage interface level of this assembly 0
SSTL2
5.0ns*1
0.7ns*1
None.
7.8µs
× 8
9
DDR SDRAM cycle time, CL = 3
SDRAM access from clock (tAC)
DIMM configuration type
Refresh rate/type
0
0
0
1
0
0
10
11
12
13
14
Primary SDRAM width
Error checking SDRAM width
None.
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0EH
04H
1CH
01H
02H
20H
2, 4, 8
4
SDRAM device attributes:
/CAS latency
2, 2.5, 3
SDRAM device attributes:
/CS latency
0
1
SDRAM device attributes:
/WE latency
Differential
Clock
SDRAM module attributes
22
23
SDRAM device attributes: General
Minimum clock cycle time at CL = 2.5
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
C0H
60H
VDD 0.2V
6.0ns*1
Maximum data access time (tAC) from
clock at CL = 2.5
24
25
26
27
28
29
30
31
32
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
70H
75H
75H
3CH
28H
3CH
28H
40H
60H
0.7ns*1
0.75ns*1
0.75ns*1
15ns
Minimum clock cycle time at CL = 2
Maximum data access time (tAC) from
clock at CL = 2
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
10ns
Minimum /RAS to /CAS delay (tRCD)
15ns
Minimum active to precharge time
(tRAS)
40ns
Module rank density
256M bytes
0.6ns*1
Address and command setup time
before clock (tIS)
Address and command hold time after
clock (tIH)
33
0
1
1
0
0
0
0
0
60H
0.6ns*1
Preliminary Data Sheet E0455E10 (Ver. 1.0)
5