EBD52UD6ADSA-E
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
18ns
Minimum /RAS to /CAS delay (tRCD)
-6B
29
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H
50H
-7A, -7B
20ns
Minimum active to precharge time
(tRAS)
-6B
30
0
0
1
0
1
0
1
0
2AH
42ns
45ns
256M bytes ×
2 ranks
-7A, -7B
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
2DH
40H
31
32
Module rank density
Address and command setup time
before clock (tIS)
-6B
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
1
0
0
0
1
0
1
75H
90H
75H
0.75ns*1
0.9ns*1
-7A, -7B
Address and command hold time after
clock (tIH)
-6B
33
0.75ns*1
-7A, -7B
1
0
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
90H
45H
50H
45H
0.9ns*1
0.45ns*1
0.5ns*1
0.45ns*1
Data input setup time before clock (tDS)
-6B
-7A, -7B
Data input hold time after clock (tDH)
-6B
-7A, -7B
34
35
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
50H
00H
0.5ns*1
36 to 40 Superset information
Future use
Active command period (tRC)
41
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
3CH
41H
60ns*1
65ns*1
-6B
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
42
0
1
0
0
1
0
0
0
48H
72ns*1
-7A, -7B
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
4BH
30H
75ns*1
12ns*1
43
44
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
2DH
32H
55H
0.45ns*1
0.5ns*1
45
0.55ns*1
-7A, -7B
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
75H
00H
00H
0.75ns*1
46 to 61 Superset information
Future use
62
SPD Revision
Checksum for bytes 0 to 62
-6B
63
0
0
0
0
1
0
0
1
09H
-7A
1
1
1
1
0
1
0
0
0
1
0
0
0
1
0
1
C0H
EBH
-7B
Continuation
code
Elpida Memory
64 to 65 Manufacturer’s JEDEC ID code
66 Manufacturer’s JEDEC ID code
67 to 71 Manufacturer’s JEDEC ID code
0
1
1
1
1
1
1
1
7FH
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH
00H
(ASCII-8bit
code)
72
Manufacturing location
×
×
×
×
×
×
×
×
××
73
74
Module part number
Module part number
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
45H
42H
E
B
Data Sheet E0604E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
