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EBD26UC6AMSA 参数 Datasheet PDF下载

EBD26UC6AMSA图片预览
型号: EBD26UC6AMSA
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB DDR SDRAM SO- DIMM [256MB DDR SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 236 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBD26UC6AMSA的Datasheet PDF文件第1页浏览型号EBD26UC6AMSA的Datasheet PDF文件第2页浏览型号EBD26UC6AMSA的Datasheet PDF文件第3页浏览型号EBD26UC6AMSA的Datasheet PDF文件第4页浏览型号EBD26UC6AMSA的Datasheet PDF文件第6页浏览型号EBD26UC6AMSA的Datasheet PDF文件第7页浏览型号EBD26UC6AMSA的Datasheet PDF文件第8页浏览型号EBD26UC6AMSA的Datasheet PDF文件第9页  
EBD26UC6AMSA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
256 bytes  
device  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
07H  
0DH  
09H  
02H  
40H  
00H  
04H  
DDR SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
13  
9
2
64 bits  
0
Module data width continuation  
Voltage interface level of this assembly  
SSTL2  
DDR SDRAM cycle time, CL = X  
-6B  
-7B  
SDRAM access from clock (tAC)  
-6B  
-7B  
9
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
60H  
75H  
70H  
CL = 2.5*1  
10  
0.7ns*1  
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H  
00H  
0.75ns*1  
None  
7.8µs  
Self refresh  
11  
12  
DIMM configuration type  
Refresh rate/type  
1
0
0
0
0
0
1
0
82H  
13  
14  
Primary SDRAM width  
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
10H  
00H  
× 16  
Error checking SDRAM width  
Not used  
SDRAM device attributes:  
Minimum clock delay back-to-back  
column access  
15  
0
0
0
0
0
0
0
1
01H  
1 CLK  
SDRAM device attributes:  
16  
17  
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0EH  
04H  
2,4,8  
4
Burst length supported  
SDRAM device attributes: Number of  
banks on SDRAM device  
18  
19  
20  
21  
22  
SDRAM device attributes: /CAS latency 0  
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0CH  
01H  
02H  
20H  
C0H  
2, 2.5  
SDRAM device attributes: /CS latency  
SDRAM device attributes: /WE latency  
SDRAM module attributes  
0
0
0
1
0
1
Unbuffered  
VDD ± 0.2V  
SDRAM device attributes: General  
Minimum clock cycle time at  
CL = X –0.5  
-6B  
23  
0
1
0
1
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
75H  
A0H  
70H  
CL = 2*1  
-7B  
Maximum data access time (tAC) from  
clock at CL = X –0.5  
-6B  
24  
0.7ns*1  
-7B  
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H  
00H  
0.75ns*1  
25 to 26  
27  
Minimum row precharge time (tRP)  
-6B  
-7B  
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H  
50H  
18ns  
20ns  
Minimum row active to row active delay  
28  
(tRRD)  
-6B  
0
0
0
0
1
1
1
1
0
1
0
1
0
0
0
0
30H  
3CH  
12ns  
15ns  
-7B  
Preliminary Data Sheet E0499E10 (Ver. 1.0)  
5