EBD12RB8ALFB
Byte No. Function described
Minimum row precharge time (tRP)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
27
28
29
30
0
1
0
1
0
0
0
0
50H
20ns
(-7A)
(-75)
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
50H
50H
20ns
20ns
(-1A)
Minimum row active to row active delay
(tRRD)
(-7A)
0
0
1
1
1
1
0
0
3CH
15ns
(-75)
(-1A)
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
3CH
3CH
15ns
15ns
Minimum /RAS to /CAS delay (tRCD)
(-7A)
0
1
0
1
0
0
0
0
50H
20ns
(-75)
(-1A)
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
50H
50H
20ns
20ns
Minimum active to precharge time
(tRAS)
(-7A)
0
0
1
0
1
1
0
1
2DH
45ns
(-75)
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
1
0
0
0
1
0
1
0
0
2DH
32H
20H
45ns
(-1A)
50ns
31
32
Module bank density
128Mbytes
Address and command setup time
before clock (tIS)
1
0
0
1
0
0
0
0
90H
0.9ns
(-7A)
(-75)
(-1A)
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
90H
B0H
0.9ns
1.1ns
Address and command hold time after
33
clock (tIH)
(-7A)
1
0
0
1
0
0
0
0
90H
0.9ns
(-75)
(-1A)
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
90H
B0H
0.9ns
1.1ns
Data input setup time before clock (tDS)
(-7A)
34
35
0
1
0
1
0
0
0
0
50H
0.5ns
(-75)
(-1A)
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
50H
60H
0.5ns
0.6ns
Data input hold time after clock (tDH)
(-7A)
0
1
0
1
0
0
0
0
50H
0.5ns
(-75)
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
50H
60H
00H
00H
0.5ns
0.6ns
(-1A)
36 to 61
62
Superset information
SPD Revision
Checksum for bytes 0 to 62
(-7A)
63
1
0
0
0
1
0
0
1
89H
(-75)
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0
B4H
5AH
FEH
00H
(-1A)
64
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s Part number
Revision code
Elpida Memory
65 to 71
72
73 to 90
91 to 92
93 to 94
95 to 98
Manufacturing date
Assembly serial number
Data Sheet E0235E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
