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EBD11RD8ADFA-7A 参数 Datasheet PDF下载

EBD11RD8ADFA-7A图片预览
型号: EBD11RD8ADFA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR SDRAM DIMM [1GB Registered DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 160 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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PRELIMINARY DATA SHEET
1GB Registered DDR SDRAM DIMM
EBD11RD8ADFA
(128M words
×
72 bits, 2 Ranks)
Description
The EBD11RD8ADFA is a 128M words
×
72 bits, 2
ranks Double Data Rate (DDR) SDRAM Module,
mounting 18 pieces of DDR SDRAM sealed in TSOP
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2-bit prefetch-
pipelined architecture. Data strobe (DQS) both for read
and write are available for high speed and reliable data
bus design. By setting extended mode register, the on-
chip Delay Locked Loop (DLL) can be set enable or
disable. This module provides high density mounting
without utilizing surface mount technology. Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 2 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0441E10 (Ver. 1.0)
Date Published December 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory,Inc. 2003