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EBD11ED8ABFA-7A 参数 Datasheet PDF下载

EBD11ED8ABFA-7A图片预览
型号: EBD11ED8ABFA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR SDRAM DIMM [1GB Unbuffered DDR SDRAM DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 192 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD10RD4ABFA  
Serial PD Matrix*1  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
128  
manufacturer  
Total number of bytes in serial PD  
device  
256 byte  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
07H  
0DH  
0CH  
01H  
48H  
00H  
04H  
SDRAM DDR  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
13  
12  
1
72 bits  
0 (+)  
Module data width continuation  
Voltage interface level of this assembly 0  
SSTL 2.5V  
DDR SDRAM cycle time, CL = X  
9
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
60H  
75H  
70H  
CL = 2.5*3  
-6B  
-7A, -7B  
SDRAM access from clock (tAC)  
-6B  
0
0
10  
0.70ns*3  
-7A, -7B  
0
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
75H  
02H  
0.75ns*3  
ECC  
7.8 µs  
Self refresh  
11  
12  
DIMM configuration type  
Refresh rate/type  
1
0
0
0
0
0
1
0
82H  
13  
14  
Primary SDRAM width  
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
04H  
04H  
× 4  
Error checking SDRAM width  
× 4  
SDRAM device attributes:  
Minimum clock delay back-to-back  
column access  
15  
0
0
0
0
0
0
0
1
01H  
1 CLK  
SDRAM device attributes:  
16  
17  
18  
19  
20  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH  
04H  
0CH  
01H  
02H  
2, 4, 8  
Burst length supported  
SDRAM device attributes: Number of  
banks on SDRAM device  
SDRAM device attributes:  
/CAS latency  
SDRAM device attributes:  
/CS latency  
SDRAM device attributes:  
/WE latency  
4
2/2.5  
0
1
21  
22  
SDRAM module attributes  
0
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
26H  
C0H  
Registered  
± 0.2V  
SDRAM device attributes: General  
Minimum clock cycle time at CLX - 0.5  
-6B, -7A  
-7B  
23  
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
75H  
A0H  
CL = 2*3  
Maximum data access time (tAC) from  
24  
clock at CLX - 0.5  
-6B  
0
1
1
1
0
0
0
0
70H  
0.70ns*3  
0.75ns*3  
-7A, -7B  
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H  
00H  
25  
26  
Minimum clock cycle time at CLX - 1  
Maximum data access time (tAC) from  
clock at CLX - 1  
0
0
0
0
0
0
0
0
00H  
Minimum row precharge time (tRP)  
-6B  
-7A, -7B  
27  
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H  
50H  
18ns  
20ns  
Preliminary Data Sheet E0274E40 (Ver. 4.0)  
5