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EBD11UD8ABFB 参数 Datasheet PDF下载

EBD11UD8ABFB图片预览
型号: EBD11UD8ABFB
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR SDRAM DIMM [1GB Unbuffered DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 207 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBD11UD8ABFB的Datasheet PDF文件第1页浏览型号EBD11UD8ABFB的Datasheet PDF文件第2页浏览型号EBD11UD8ABFB的Datasheet PDF文件第3页浏览型号EBD11UD8ABFB的Datasheet PDF文件第4页浏览型号EBD11UD8ABFB的Datasheet PDF文件第6页浏览型号EBD11UD8ABFB的Datasheet PDF文件第7页浏览型号EBD11UD8ABFB的Datasheet PDF文件第8页浏览型号EBD11UD8ABFB的Datasheet PDF文件第9页  
EBD11UD8ABFB  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
256 bytes  
device  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
07H  
0DH  
0BH  
02H  
40H  
00H  
04H  
DDR SDRAM  
Number of row address  
Number of column address  
Number of DIMM banks  
Module data width  
13  
11  
2
64  
Module data width continuation  
0
Voltage interface level of this assembly 0  
SSTL2  
DDR SDRAM cycle time, CL = 2.5  
9
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
60H  
75H  
70H  
6.0ns*1  
7.5ns*1  
0.7ns*1  
-6B  
-7A, -7B  
SDRAM access from clock (tAC)  
-6B  
0
0
10  
-7A, -7B  
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
75H  
00H  
82H  
08H  
00H  
0.75ns*1  
None.  
7.6µs  
× 8  
11  
12  
13  
14  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
None.  
SDRAM device attributes:  
Minimum clock delay back-to-back  
column access  
15  
0
0
0
0
0
0
0
1
01H  
1 CLK  
SDRAM device attributes:  
16  
17  
18  
19  
20  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH  
04H  
0CH  
01H  
02H  
2,4,8  
Burst length supported  
SDRAM device attributes: Number of  
banks on SDRAM device  
SDRAM device attributes:  
/CAS latency  
SDRAM device attributes:  
/CS latency  
SDRAM device attributes:  
/WE latency  
4
2, 2.5  
0
1
Differential  
Clock  
VDD ± 0.2V  
21  
22  
23  
SDRAM module attributes  
0
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
20H  
C0H  
75H  
A0H  
SDRAM device attributes: General  
Minimum clock cycle time at CL = 2  
-6B, -7A  
7.5ns*1  
-7B  
10ns*1  
Maximum data access time (tAC) from  
24  
clock at CL = 2  
-6B  
0
1
1
1
0
0
0
0
70H  
0.7ns*1  
-7A, -7B  
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
75H  
00H  
0.75ns*1  
25 to 26  
27  
Minimum row precharge time (tRP)  
-6B  
-7A, -7B  
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
48H  
50H  
18ns  
20ns  
Preliminary Data Sheet E0296E20 (Ver. 2.0)  
5