EBD11UD8ADFB
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
12ns
Minimum row active to row active
delay (tRRD)
-6B
28
29
30
0
0
1
1
0
0
0
0
30H
-7A, -7B
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
3CH
48H
50H
15ns
18ns
20ns
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
(tRAS)
-6B
0
0
1
0
1
0
1
0
2AH
42ns
-7A, -7B
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
2DH
80H
45ns
31
32
Module rank density
512M bytes
Address and command setup time
before clock (tIS)
-6B
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
75H
90H
75H
90H
45H
0.75ns*1
0.9ns*1
-7A, -7B
Address and command hold time after
clock (tIH)
-6B
33
0.75ns*1
0.9ns*1
-7A, -7B
Data input setup time before clock
(tDS)
-6B
34
35
0.45ns*1
-7A, -7B
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
50H
45H
0.5ns*1
Data input hold time after clock (tDH)
-6B
-7A, -7B
0.45ns*1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
50H
00H
0.5ns*1
36 to 40
41
Superset information
Active command period (tRC)
-6B
Future use
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
3CH
41H
60ns*1
65ns*1
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
42
0
1
0
0
1
0
0
0
48H
72ns*1
-7A, -7B
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
4BH
30H
75ns*1
12ns*1
43
44
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
2DH
32H
55H
450ps*1
500ps*1
550ps*1
45
-7A, -7B
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
75H
00H
00H
750ps*1
46 to 61
62
Superset information
SPD Revision
Future use
Checksum for bytes 0 to 62
-6B
63
0
1
0
0
0
0
1
0
42H
-7A
1
0
1
0
1
1
1
0
1
0
0
1
0
0
1
0
F9H
24H
-7B
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
0
1
1
1
1
1
1
1
7FH
Data Sheet E0414E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
