EBD10RD4ABFB
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal)
SDRAM
stack
PLL
120Ω
OUT1
SDRAM
stack
120Ω
CK0
IN
240Ω
Register1
/CK0
(Typically two registers per DIMM)
OUT'N'
120Ω
C
Feedback
Register2
240Ω
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0 ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Preliminary Data Sheet E0400E10 (Ver. 1.0)
8
ELPIDA [ ELPIDA MEMORY ]
