GD25LQ256CWIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25LQ256C provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
♦
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
- Erase Security Registers / Program Security Registers
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
♦
♦
Table 1. GD25LQ256C Protected area size (CMP=0)
Status Register Content
BP4 BP3 BP2 BP1 BP0
Memory Content
Addresses
Blocks
NONE
Density
NONE
512KB
1MB
Portion
NONE
×
0
0
0
0
0
0
0
0
0
0
0
0
×
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
NONE
504 to 511
495 to 511
479 to 511
447 to 511
384 to 511
256 to 511
0 to 7
1F80000H-1FFFFFFH
1F00000H-1FFFFFFH
1E00000H-1FFFFFFH
1C00000H-1FFFFFFH
1800000H-1FFFFFFH
1000000H-1FFFFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
000000H-7FFFFFH
000000H-0FFFFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
2MB
4MB
8MB
16MB
512KB
1MB
0 to 15
0 to 31
2MB
0 to 63
4MB
0 to 127
0 to 255
8MB
16MB
Rev.1.0
68 - 8
ELM [ ELM ELECTRONICS ]
