GD25LQ16xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25LQ16 provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
♦
- Power-Up / Write Disable (WRDI) / Write Status Register (WRSR)
- Page Program (PP) / Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
♦
♦
Table 1. GD25LQ16 Protected area size (CMP=0)
Status Register Content
BP4 BP3 BP2 BP1 BP0
Memory Content
Addresses
Blocks
NONE
31
30 to 31
28 to 31
24 to 31
16 to 31
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
31
Density
NONE
64KB
128KB
256KB
512KB
1MB
64KB
128KB
256KB
512KB
1MB
2MB
4KB
8KB
16KB
32KB
4KB
8KB
16KB
32KB
Portion
NONE
×
0
0
0
0
0
0
0
0
0
0
×
1
1
1
1
1
1
1
1
×
0
0
0
0
0
1
1
1
1
1
×
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
×
1
0
1
×
1
0
1
×
NONE
1F0000H-1FFFFFH
1E0000H-1FFFFFH
1C0000H-1FFFFFH
180000H-1FFFFFH
100000H-1FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
1FF000H-1FFFFFH
1FE000H-1FFFFFH
1FC000H-1FFFFFH
1F8000H-1FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
31
31
31
0
0
0
0
Rev.1.0
59 - 8
ELM [ ELM ELECTRONICS ]
