Spec. No. : C705P8
Issued Date : 2007.08.23
Revised Date :
CYStech Electronics Corp.
Page No. : 8/12
Device Addressing
To enable the chip for a read or write operation, an 8-bit device address word followed by a START
condition must be issued. The 1st four bits of the device address word consist of a mandatory ‘1010’pattern,
while the 2nd four bits depend on the particular density being used(refer to Figure 6):
●In the 1K/2K chip, the next 3 bits should correspond to the hard-wired input A2, A1, and A0 device
address bits.
●In the 4K chip, the next 3 bits are the A2 and A1 device address bits and a memory page address bit.
The two device address bits must compare to their corresponding hard-wired input pins.
●In the 8K chip, the next 3 bits include the A2 device address bit with the next 2 bits used for memory
page addressing. The A2 bit must compare to its corresponding hard-wired input pin.
●The 16K chip does not use any device address bits but instead the 3 bits are used for memory page
addressing.
Figure 6. Device address
The memory page address bits , P2, P1, and P0 are used to select the page in the array. P2 represents the
most significant bit, while P1 and P0 are considered the next most significant bits.
The eight bit of the device address determines read or write operation. If the R/W bit is high, then a read
operation is initiated. Otherwise, if the R/W bit is low, then a write operation is started.
After comparing the device address and finding a match, the EEPROM device will issue an acknowledge-
ment by pulling SDA low. If the comparison fails, the chip will return to standby mode.
Figure 7. Byte Write
CTK24BC01-16P8
CYStek Product Specification
CYSTEKEC [ CYSTECH ELECTONICS CORP. ]
