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CTK24BC01-16Q8 参数 Datasheet PDF下载

CTK24BC01-16Q8图片预览
型号: CTK24BC01-16Q8
PDF下载: 下载PDF文件 查看货源
内容描述: [2-Wire Serial EEPROMs 1K/2K/4K/8K/16K]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 12 页 / 376 K
品牌: CYSTEKEC [ CYSTECH ELECTONICS CORP. ]
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Spec. No. : C705Q8  
Issued Date : 2007.08.22  
Revised Date :  
CYStech Electronics Corp.  
Page No. : 5/12  
AC Characteristics(Cont.)  
Applicable over recommended operating range: TA=-40~+85, VCC=+1.8V~+5.0V, CL=1TTL Gate & 100pF(unless otherwise noted)  
Parameter  
Stop Setup Time  
Symbol  
tSU.STO  
Condition  
VCC=1.8V  
VCC=2.7~5.5V  
VCC=1.8V  
VCC=2.7~5.5V  
VCC=1.8V  
VCC=2.7~5.5V  
VCC=1.8V  
VCC=2.7~5.5V  
Min. Typ. Max.  
4.7  
Unit  
-
-
-
-
-
μs  
0.6  
100  
50  
Data out Hold Time  
Write Cycle Time  
tDH  
-
ns  
5
5
tWR  
-
ms  
1M  
1M  
Write  
Cycles  
Endurance  
(Note 1)  
5.0V, 25, Byte Mode  
-
Note: 1. This parameter is characterized and not 100% tested.  
Device Operation  
Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low(refer to the  
Data Validity timing diagram in Figure 3). If the SDA pin changes when SCL is high, then the transition  
will be interpreted as a START or STOP condition.  
START Condition: A START condition occurs when the SDA transitions from high to low when SCL is  
high. The START signal is usually used to initiate a command(refer to the START and STOP definition  
timing diagram in Fig 4)  
STOP Condition: A STOP condition occurs when the SDA transitions from low to high when SCL is high.  
(refer to the START and STOP definition timing diagram in Fig 4) The STOP command will put the device  
into standby mode after no acknowledgement is issued during the read sequence.  
Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been  
successfully received. All addresses and data words are serially transmitted to and from the EEPROM in  
8-bit words, so acknowledgements are usually issued during the 9th clock cycle.  
Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command  
has been issued and any internal operations have been completed.  
Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to  
restart the input command sequence. If the device is currently in write cycle mode, this command will be  
ignored.  
CTK24BC01-16Q8  
CYStek Product Specification