+/+…when timing is critical
C9836
Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
Power Management Timing
0ns
10ns
20ns
30ns
40ns
50ns
60ns
CPU 100 MHz
3V66 66 MHz
PCI 33 MHz
PD#
SDRAM 100 MHz
REF 14.3 MHz
Figure 1
Power Management Current
Maximum 2.5 Volt Current
Consumption (VDDC = 2.625V)
Maximum 3.3 Volt Current Consumption
(VDD = AVDD = VDDS = 3.465V)
CONDITIONS
Power down (PD# = LOW)
CPU=66MHz @ max loads
CPU=100MHz @ max loads
CPU=133MHz @ max loads
< 1mA
< 1mA
60mA (Preliminary)
75mA (Preliminary)
160mA (Preliminary)
160mA (Preliminary)
160mA (Preliminary)
90mA (Preliminary)
Table 3
When exiting the power down mode, the application must supply power to the VDD pins a minimum of 200ms before
releasing the PD# pin high to insure that an orderly startup will occur and that the initial clocks that the device produces
are full and correctly compliant with data sheet specified phase relationships.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
3/30/2000
Page 4 of 20
CYPRESS [ CYPRESS ]
