+/+…when timing is critical
C9829B
Low EMI Clock Generator for Intel 133MHz/3DIMM Chipset Systems
Approved Product
Group Timing Relationships and Tolerances
CPU = 66.6 MHz, SDRAM = 100 MHz
Offset (nS)
Tolerance (pS)
Conditions
CPU to SDRAM
CPU to 3V66
2.5
7.5
500
500
180 degrees phase shift
When rising edges line-up
3V66 leads
SDRAM to 3V66
3V66 to PCI
0
500
1.5-3.5
0
500
PCI to IOAPIC
1000
CPU = 100 MHz, SDRAM = 100 MHz
Offset (nS)
Tolerance (pS)
Conditions
CPU to SDRAM
CPU to 3V66
5
500
500
500
500
1000
180 degrees phase shift
5
SDRAM to 3V66
3V66 to PCI
0
1.5-3.5
0
When rising edges line-up
3V66 leads
PCI to IOAPIC
CPU = 133.3 MHz, SDRAM = 100 MHz
Offset (nS)
Tolerance (pS)
Conditions
CPU to SDRAM
CPU to 3V66
0
500
500
500
500
1000
When rising edges line-up
0
SDRAM to 3V66
3V66 to PCI
0
1.5-3.5
0
When rising edges line-up
3V66 leads
PCI to IOAPIC
CPU = 133.3 MHz, SDRAM = 133.3 MHz
Offset (nS)
Tolerance (pS)
Conditions
CPU to SDRAM
CPU to 3V66
3.75
0
500
500
500
500
1000
180 degrees phase shift
SDRAM to 3V66
3V66 to PCI
3.75
1.5-3.5
0
3V66 leads
PCI to IOAPIC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.3
4/12/2000
Page 5 of 20
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