+/+…when timing is critical
C9825B
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
Preliminary
Pin Description
PIN No.
Pin Name
PWR
VDDI
VDD
I/O TYPE
O
I/O PD
Description
47
2
2.5V IOAPIC clock output. See fig.3 p.4 for timing relationship.
This is a bi-directional pin (see app. note, p.5). At power up, it
is an input pin Sel1 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of Sel1 is latched,
and this pin becomes REF, a buffer output of the signal applied
at Xin, typically 14.318MHz.
IOAPIC
SEL1 / REF
4
VDD
VDD
VDD
I
OSC1 On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
XIN
5
O
On-chip reference oscillator pin. Drives an external parallel
resonant crystal. When an externally generated reference
signal is used at Xin, this pin remains unconnected.
This is a bi-directional pin (see app. note, p.5). At power up, it
is an input pin Sel3 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of Sel3 is latched,
and this pin becomes PCI clock output.
XOUT
12
I/O PD
SEL3 / PCI0
13,14,17,18,
19
VDD
O
3.3V PCI clock outputs. They are Synchronous to CPU clocks.
See fig.3, page4.
PCI(1:5)
8, 9, 10
27
VDD
VDD
O
3.3V Hub/AGP clock outputs. See fig.3 page 3.
This is a bi-directional pin (see app. note, p.5). At power up, it
is an input pin Sel2 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of Sel2 is latched,
and this pin becomes a fixed 48MHz clock output for USB.
3.3V Fixed 48 MHz DOT clock output
3.3V LVTTL inputs for frequency selection, see table 1 page 1.
Serial data input pin. Conforms to the Philips I2C specification
of a Slave Receive/Transmit device. This pin is an input when
receiving data. It is an open drain output when acknowledging
or transmitting data. See I2C function description, pp. 8,9.
Serial clock input pin. Conforms to the Philips I2C specification.
3.3V SDRAM DIMM clocks. See table1, p.1 for frequency
selection. See fig.3, page 3 for timing relationship and I2C
Byte3, Bit0.
3V66(0:2)
SEL2 / USB
I/O PD
28
20
24
VDD
VDD
VDD
O
I
I
DOT
SEL0
SDATA
PU
23
VDD
VDDS
I
O
SCLK
SDRAM
(0:8)
29,30,31,34,
35,36,37,40,
41
43,44
3,7,15,22,26
45, 48
1,6,11,16,21,
25, 32, 38,
42, 46
VDDC
O
2.5V Host clock outputs. See table1, p1 for frequency selection.
3.3V Common Power Supply
2.5V Power Supply for CPU(0:1) and IOAPIC respectively.
Common Ground pins.
CPU(0:1)
VDD
VDDC,VDDI
VSS
-
-
-
-
-
39,33
-
3.3V power support for SDRAM(0:8) clock output drivers.
VDDS
PU = Internal Pull-Up. Typical 250KΩ (range 200KΩ to 500KΩ). PD = Internal Pull-Down. Typical 50KΩ (range 20KΩ to 70KΩ)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/12/2000
Page 2 of 18
CYPRESS [ CYPRESS ]
