C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Serial Control Registers (Cont.)
Byte 1: Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
@Pup
1
0
Pin#
-
10
Description
0= Test Mode ( XIN replaces VCO output ), 1=Normal
Bit 6 Bit 5 PCI9 Frequency
-----------------------------------------
5
HW
10
0
0
1
1
0
1
0
1
33 MHz
66 Mhz
16.5 Mhz
8.25 MHz
4
3
2
1
0
0
HW
0
1
1
27
27
-
10
11
REF-CLK0 mode ( 1 = REF, 0 = PCI0 )
CLK0 (33.3 MHz = 0, 66.6 MHz = 1)(if Byte 3 Bit 4=0)
SSCG (OFF = 0, ON = 1)
CLK9 ( Active = 1, Forced low = 0 )
CLK8 ( Active = 1, Forced low = 0 )
Byte 2: Clock Register (1 = 66.6 MHz, 0 = 33.3 MHz)
Bit
7
6
5
4
3
2
1
0
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Pin#
11
14
15
18
19
22
23
26
Description
CLK8 (33.3 MHz = 0, 66.6 MHz = 1)
CLK7 (33.3 MHz = 0, 66.6 MHz = 1)
CLK6 (33.3 MHz = 0, 66.6 MHz = 1)
CLK5 (33.3 MHz = 0, 66.6 MHz = 1)
CLK4 (33.3 MHz = 0, 66.6 MHz = 1)
CLK3 (33.3 MHz = 0, 66.6 MHz = 1)
CLK2 (33.3 MHz = 0, 66.6 MHz = 1)
CLK1 (33.3 MHz = 0, 66.6 MHz = 1)
Note: HW = Power up programmed via hardware (voltage at pin).
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07014 Rev. **
5/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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