ADVANCE
CYW43570
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43570. All regulators
are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
A single VBAT1 (3.0V to 3.6V maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by
the regulators in the CYW43570.
Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of
reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only
when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic
demands of the digital baseband.
The CYW43570 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO
supply) provide the CYW43570 with all the voltages it requires, further reducing leakage currents.
Figure 3 shows a typical power topology.
2.2 CYW43570 PMU Features
■ VBAT to 1.35Vout (550 mA nominal, 870 mA maximum) Core-Buck (CBUCK) switching regulator
■ VBAT to 2.5V out (15 mA nominal, 70 mA maximum) BTLDO2P5
■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
■ 1.35V to 1.2Vout (350 mA nominal, 500 mA maximum) CLDO with bypass mode for deep-sleep
■ Additional internal LDOs (not externally accessible)
1. VBAT is the main power supply (ranges from 3.0V to 3.6V) to the chip.
Document Number: 002-15054 Rev. *I
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