CYW4354
Figure 2. CYW4354 Block Diagram
CYW4354
JTAG
WLAN
BT/FM
*SDIO or *PCIe 2.0
FMRX
PCIe
Debug
Cortex M3
AHB
PMU
Controller
SW REG
LDO
HSIC
SDIO
FM RX
FM RF
FM Digital
Power Supply
XTAL
LPO
XTAL OSC
POR
RAM
ROM
AHB2 APB
Bridge
APB
Patch
OTP
OTP
WD Timer
SW Timer
GPIO Ctrl
Inter Ctrl
DMA
ARM
GPIO
UART
JTAG
GPIO
UART
JTAG
Bus Arb
PTU
UART
SLIMBus
AHB
RAM
ROM
Debug UART
MEIF
BT RF
BT PHY
5 GHz IPA
CLB
I2S/PCM1
I2S/PCM2
BPF
LNA
2.4 GHz IPA
Diplexer
BT Digital IO
BPF
BPF
GPIO
LNA
5 GHz IPA
SMPS Control
BTFM Control Clock
Sleep
Clock
PMU
Controller
GNSS LNA ANT
Control
PMU
Timer Management
LNA
Diplexer
2.4 GHz IPA
Wake/Sleep
Control
BT‐WLAN ECI
XO
LPO
BPF
POR
Coex
Buffer
Shared LNA
BT RX
BT TX
VBAT VREG
EXT LNA RF Switch Control
XTAL
POR
Document Number: 002-14809 Rev. *J
Page 7 of 165
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