PRELIMINARY
CYW43438
1. Overview
1.1 Overview
The Cypress CYW43438 provides the highest level of integration for a mobile or handheld wireless system, with integrated
IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes
and allows for handheld device flexibility in size, form, and function. The CYW43438 is designed to address the needs of highly mobile
devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnection of all the major physical blocks in the CYW43438 and their associated external interfaces, which
are described in greater detail in subsequent sections.
Figure 2. CYW43438 Block Diagram
Cortex
Debug
M3
AHB
FMRX
FMRF
FMDigital
AHB to APB
Bridge
ADC
ADC
FM
I/F
RAM
ROM
FMDemod.
MDX RDS
Decode
LNA
APB
FM_RX
Patch
InterCtrl
DMA
WD Timer
SWTimer
Control
LO
Gen.
RSSI
DPLL
Bus Arb
ARMIP
GPIO
Ctrl
JTAGsupported over SDIO or BT PCM
SDIO or gSPI
SWREG
LDOx2
LPO
XTAL OSC.
POR
Power
Supply
Sleep CLK
XTAL
BPL
UART
PMU
Control
Buffer
SDIO
gSPI
Modem
RF
Digital
Demod.
&Bit
APU
WL_REG_ON
Debug
UART
BT Clock/
Hopper
Sync
ARM
CM3
WDT
OTP
Digital
I/O
BlueRF
Interface
PA
Digital
Mod.
PCM
GPIO
UART
JTAG*
GPIO
UART
LCU
RAM
Supported over SDIO or BT PCM
RX/TX
Buffer
ROM
GPIO
IF
PLL
BT PHY
BT‐WLAN
ECI
Wake/
Sleep Ctrl
BTFMClock Control
Clock
WiMax Coex
2.4 GHz
PA
Sleep‐
time
Keeping
PMU
Ctrl
PMU
Management
Shared LNA
BPF
WiMax
Coex.
XO
Buffer
LPO
POR
WLAN
PTU
*Via GPIO configuration, JTAGis supported over SDIO or BT PCM
Document Number: 002-14796 Rev. *K
Page 5 of 101
CYPRESS [ CYPRESS ]
